Semiconductor device comprising a passive component of capacitors and process for fabrication

ABSTRACT

A semiconductor device includes a wafer having a frontside and a backside. The wafer is formed from at least one integrated circuit chip having an electrical connection frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. A passive component including at least one conductive plate and a dielectric plate is positioned adjacent the integrated circuit chip. An encapsulation block embeds the integrated circuit chip and the passive component, the block having a frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. An electrical connection is made between the electrical connection frontside and the passive component. That electrical connection includes connection lines placed on the wafer frontside and wafer backside. The electrical connection further includes at least one via passing through the encapsulation block.

PRIORITY CLAIM

This application is a divisional application of U.S. application patentSer. No. 13/179,640 filed on Jul. 11, 2011, which claims priority fromFrench Application for Patent No. 1056159 filed Jul. 27, 2010, thedisclosures of which are hereby incorporated by reference.

TECHNICAL FIELD

This disclosure relates to the field of semiconductor devices.

BACKGROUND

It is known to produce reconstituted wafers comprising, in locations,integrated circuit chips embedded in an encapsulation material and tosaw these wafers so as to form individual semiconductor devices.

Nevertheless, it is not possible at the present time to integrate intothe wafers, near the chips, capacitors such as those currently used,especially due to their shape and their electrical connection means.

SUMMARY

A process for fabricating a semiconductor device is provided.

This process comprises: placing, in at least one location on a receivingsurface of a carrier, an electrical connection frontside of at least oneintegrated circuit chip and a frontside of at least one passivecomponent comprising conductive plates separated by dielectric platesforming capacitors; forming on the receiving surface a layer of anencapsulation material so as to obtain, in the location, a wafercomprising an encapsulation block in which the chip and the passivecomponent are embedded and having a frontside comprising the frontsideof the chip and the frontside of the passive component; then selectivelyconnecting at least some of the conductive plates to the chip, so thatat least some of the capacitors are connected to the chip.

It is thus possible to prefabricate a passive component having a simplestructure, to integrate it into the encapsulation block, and then toform one or more capacitors, as required, when electrical connectionsare made to the chip.

The process may comprise: forming at least one front electricalconnection track on the frontside of the wafer.

The process may comprise: forming at least one back electricalconnection track on the backside of the wafer, an electrical connectionvia through the wafer and a front electrical connection track on thefrontside of the wafer, the back track and the front track beingconnected by the electrical connection via.

The process may comprise: placing the passive component such that theplates extend perpendicularly to the receiving surface, then selectivelyconnecting at least some of the lands of the conductive plates to thechip.

The process may comprise: placing the passive component such that theplates extend parallel to the receiving surface.

The process may comprise: placing a passive component having adielectric plate on the receiving surface, then forming at least oneadditional conductive plate on the frontside of this dielectric plate soas to form a capacitor comprising this conductive plate and the adjacentconductive plate of the passive component, which are separated by thisfirst dielectric plate.

A semiconductor device is also provided, which comprises a wafer havinga frontside and comprising at least one integrated circuit chip havingan electrical connection frontside, at least one passive componenthaving a frontside and comprising conductive plates separated bydielectric plates, forming capacitors, and an encapsulation block inwhich the integrated circuit chip and the passive component areembedded, a frontside of the encapsulation block, the frontside of theintegrated circuit chip and the frontside of the passive componentforming the frontside of the wafer, and an electrical connection meansconnecting at least some of the conductive plates and the integratedcircuit chip, the electrical connection means being formed on thefrontside of the wafer and/or on the backside of the wafer through theencapsulation block and on the frontside of the wafer.

The passive component may comprise plates which extend perpendicularlyto the frontside of the wafer, the electrical connection means beingconnected to the lands of the conductive plates.

The plates may extend through the thickness of the wafer.

The passive component may comprise plates which extend parallel to thefrontside of the wafer.

The passive component may comprise a dielectric plate adjacent to thefrontside of the wafer, at least one conductive plate being formed onthe frontside of this dielectric plate.

BRIEF DESCRIPTION OF THE DRAWINGS

Semiconductor devices will now be described by way of non-limitingexample, illustrated by the drawings in which:

FIG. 1 shows a cross section of a semiconductor device;

FIG. 2 shows a front view of the semiconductor device in FIG. 1, withouta surface layer;

FIG. 3 shows a perspective view of a passive component of thesemiconductor device in FIG. 1;

FIG. 4 shows the semiconductor device in FIG. 1, according to onefabrication step;

FIG. 5 shows the semiconductor device in FIG. 1, according to anotherfabrication step;

FIG. 6 shows the semiconductor device in FIG. 1, according to anotherfabrication step;

FIG. 7 shows the semiconductor device in FIG. 1, according to anotherfabrication step;

FIG. 8 shows a cross section of another semiconductor device;

FIG. 9 shows a front view of the semiconductor device in FIG. 8, withouta surface layer;

FIG. 10 shows a perspective view of a passive component of thesemiconductor device in FIG. 8;

FIG. 11 shows the semiconductor device in FIG. 8, according to onefabrication step;

FIG. 12 shows the semiconductor device in FIG. 8, according to anotherfabrication step;

FIG. 13 shows the semiconductor device in FIG. 8, according to anotherfabrication step; and

FIG. 14 shows the semiconductor device in FIG. 8, according to anotherfabrication step.

DETAILED DESCRIPTION

A semiconductor device 1 illustrated in FIGS. 1 to 3 comprises a wafer 2which has a frontside 3 and a backside 4, in parallel.

The wafer 2 comprises a block of a dielectric encapsulation material 5in which a prefabricated integrated circuit chip 6 and a prefabricatedpassive component 7 are embedded, these being placed so that a frontside8 of the chip 6, in which the integrated circuits are formed and whichhas electrical connection pads, a frontside 9 of the passive component 7and a frontside 10 of the encapsulation block 5 are in the same planeforming the frontside 3 of the wafer 2, the passive component 7 beingplaced at a distance to the side of the chip 6. Thus, the frontside 8 ofthe chip 6 and the frontside 9 of the passive component 7 are notcovered by the encapsulation block 5.

The passive component 7 comprises a plurality of superposed plates,which are placed parallel to the frontside 3 of the wafer 2. Accordingto the example shown, the passive component 7 comprises in succession,in the thickness direction of the wafer 2, a dielectric plate 11 havingthe aforementioned side 9, a conductive plate 12, a dielectric plate 13and a conductive plate 14, the conductive plates 12 and 14 being forexample metallic. The plate 12 completely covers the plate 11, the plate13 does not completely cover the plate 12 and the plate 14 completelycovers the plate 13, the conductive plate 14 being, in the exampleshown, distant from the backside 4 of the wafer 2.

On the frontside 3 of the wafer 2, two conductive front plates 15 and 16are formed, which are connected to electrical connection pads on thefrontside 8 of the chip 6 by front electrical connection tracks 17 and18, the conductive plates 15 and 16 being located on the frontside 9 ofthe dielectric plate 11 and being distant from each other. Theconductive front plates 15 and 16 have the same thickness as the frontelectrical connection tracks 17 and 18.

Behind the plates 12 and 14, and between the plates 12 and 14 and thebackside 4 of the wafer 2, holes 19 and 20 are provided in theencapsulation block 5, which are filled with a conductive material so asto form electrical connection vias 21 and 22.

According to one variant, the passive component 7 could have the samethickness as the wafer 2. In this case, the electrical connection via 22could be omitted.

To the side of the chip 6 and the passive component 7, and between thefrontside 3 and the backside 4 of the wafer 2, through-holes 23 and 24are provided in the encapsulation block 5 and are filled with aconductive material so as to form electrical connection vias 25 and 26.

On the frontside 3 of the wafer 2, front electrical connection tracks 27and 28 are formed connecting the vias 25 and 26, respectively, toelectrical connection pads on the frontside 8 of the chip 6 and, on thebackside 4 of the wafer 2, back electrical connection tracks 29 and 30are formed connecting the vias 21 and 22 to the vias 25 and 26,respectively.

Thus, the passive component 7 defines three capacitors connected to thechip 6, namely a first capacitor C1 comprising the conductive plate 12and the conductive plate 15 which are separated by the dielectric plate11, a second capacitor C2 comprising the conductive plate 12 and theconductive plate 16 which are separated by the dielectric plate 11, anda third capacitor C3 comprising the conductive plates 12 and 14 whichare separated by the dielectric plate 13.

On the frontside 3 of the wafer 2, and covering the conductive plates 15and 16 and the electrical connection tracks 17, 18, 27 and 28, adielectric layer 31 is provided, incorporating an electrical connectionnetwork 32 allowing electrical connection pads, on the frontside 8 ofthe chip 6, and external electrical connection bumps 33, placed on afrontside of the layer 31, to be selectively connected.

A protective dielectric layer 34 is provided on the backside 4 of thewafer 2, covering the electrical connection tracks 29 and 30.

The semiconductor device 1 may be produced in the following way, bysuitably employing means used in the microelectronics field.

As illustrated in FIG. 4, in respective adjacent, for example square,locations 35 in a receiving surface 36 of a carrier 37, chips 6 andpassive components 7 are placed, their frontsides 8 and 9 being placedagainst the receiving surface 36, the receiving surface 36 being forexample self-adhesive.

As illustrated in FIG. 5, an encapsulation layer 38 is formed on thereceiving surface 36 of the carrier 37, embedding the chips 6 and thepassive components 7 and layer 38 is then leveled or thinned, forexample as far as the backside of the chips 6, so as to obtain a largereconstituted wafer 39 forming, respectively in the locations 35,encapsulation blocks 5 holding chips 6 and passive components 7.

In FIG. 6, holes 19, 20, 23 and 24 are produced, respectively in thelocations 35, and in the encapsulation layer 38 and these holes arefilled with a conductive material so as to form vias 21, 22, 25 and 26,respectively, in the encapsulation blocks 5.

In FIG. 7 and more fully shown in FIG. 1, the layer 31 is produced onthe frontside 3 of the wafer 2, incorporating therein, respectively inthe locations 35, and on the same metallization level, the conductiveplates 15 and 16, the front electrical connection tracks 17, 18, 27 and28, and the electrical connection network 32. An intermediate dielectriclayer could be formed directly on the frontside of the wafer 2, theconductive plates 15 and 16, the front electrical connection tracks 17,18, 27 and 28 and the electrical connection network 32 then beingproduced on this intermediate dielectric layer and passing through thelatter in places where electrical connection is required. Moreover, theelectrical connection network 32 could nevertheless comprise severalmetallic levels.

On the backside 4 of the wafer 2, the layer 34 is produced,incorporating therein, in the locations 35 respectively, and on the samemetallization level, the back electrical connection tracks 29 and 30.

The electrical connection bumps 33 are placed on the front layer 31.

Finally, the large wafer 39 obtained is singulated, along the edges ofthe location 35, for example by sawing, so as to obtain a plurality ofsemiconductor devices 1.

When the conductive front plates 15 and 16 are produced, at the sametime as the front electrical connection tracks 17 and 18, thecapacitances of the capacitors C1 and C2 are defined, especially bychoosing the areas of these plates 15 and 16. Of course, one or morecapacitors could be produced by forming one or more conductive plates onthe frontside 3, at the same time as one or more tracks for electricalconnection to the chip 6.

In addition, being provided with a prefabricated passive componentcomprising several capacitors, only some of the capacitors could beconnected, as a function of the chip 6 used and of the requirementsrelated to the operation and applications of the latter.

Another semiconductor device 50, illustrated in FIGS. 8-10, comprises awafer 51 which has a frontside 52 and a backside 53, in parallel.

The wafer 51 comprises a block of an encapsulation material 54 in whicha prefabricated integrated circuit chip 55 and a prefabricated passivecomponent 56 are embedded, these being placed so that an electricalconnection frontside 57 of the chip 55, a frontside 58 of the passivecomponent 56, and a frontside 59 of the encapsulation block 5 are in thesame plane formed by the frontside 52 of the wafer 51, the passivecomponent 56 being placed at a distance to the side of the chip 55.

The passive component 56 comprises a plurality of superposed plates,placed perpendicular to the frontside 52 of the wafer 51. According tothe example shown, the passive component 56 comprises four parallel, forexample metallic, conductive plates 60, 61, 62 and 63, separated bythree dielectric plates 64, 65 and 66, so as to form three capacitorsC10, C11 and C12.

The conductive plates 60-63 and the dielectric plates 64-66 are placedso as to have front lands which form the side 58 of the passivecomponent 56 in the plane of the frontside 57 of the wafer 51, andopposite back lands which are in the plane of the backside 53 of thewafer 51, the conductive plates 60-63 and the dielectric plates 64-66consequently having, between these opposite lands, a width correspondingto the thickness of the wafer 51.

By way of example, the capacitors C10-C12 may be connected to the chip55 in the following way.

For example, front electrical connection tracks 67, 68 and 69 may beformed on the frontside 52 of the wafer 51 so as to connect the frontlands of the conductive plates 60, 61 and 62 to front pads of the chip55, by extending onto these front lands and onto these pads, so that thecapacitors C10 and C11 are connected to the chip 55 by the front tracks67 and 68 and by the front tracks 68 and 69, respectively.

Furthermore, the encapsulation block 54 may have a through-hole 70filled with a material forming an electrical connection via 71, a frontelectrical connection track 72 possibly being formed on the frontside 52of the wafer 51 so as to connect the via 71 and a front pad of the chip55, by extending over this via and this pad, and a back electricalconnection track 73 possibly being formed on the backside 53 of thewafer 51 so as to connect the via 71 and the back land of the conductiveplate 63, by extending over this via and this land, so that thecapacitor C12 is connected to the chip 55 by the via 71, the frontelectrical connection track 72 and the back electrical connection track73.

On the frontside 52 of the wafer 51, and covering the frontside of thepassive component 56 and the front electrical connection tracks 67-69and 72, a dielectric layer 74 is provided, incorporating an electricalconnection network 75 allowing electrical connection pads, on thefrontside 57 of the chip 55, and external electrical connection bumps76, placed on a frontside of the layer 74, to be selectively connected.

A protective dielectric layer 77 is provided on the backside 53 of thewafer 51, covering the backside of the passive component 56 and the backelectrical connection track 73.

The semiconductor device 50 may be produced in the following way.

In FIG. 11, in respective adjacent locations 78 (e.g., squares) in areceiving surface 79 of a carrier 80, chips 55 and passive components 56are placed, their frontsides 57 and 58 being placed against thereceiving surface 79, the receiving surface 79 being for exampleself-adhesive.

In FIG. 12, an encapsulation layer 81 is formed on the receiving surface79 of the carrier 80, embedding the chips 55 and the passive components56 and the layer 81 is then leveled or thinned, until the backsides ofthe passive components 56 are exposed, so as to obtain a largereconstituted wafer 82 forming, respectively in the locations 78,encapsulation blocks 54 holding chips 55 and passive components 56.

In FIG. 13, a hole 70 is produced, respectively in the locations 78, inthe encapsulation layer 81 and this hole 70 is filled with a conductivematerial so as to form the via 71, respectively, in the encapsulationblocks 54.

In FIG. 14 and more fully shown in FIG. 8, and in a way equivalent tothat described above, with reference to FIGS. 1 and 7, in relation tothe device 1, on the one hand, front electrical connection tracks 67,68, 69 and 72 and the network 75 are produced, respectively in thelocations 78, in the dielectric front layer 74 and, on the other hand,the back electrical connection track 73 is produced in the dielectricback layer 77.

Then the bumps 76 are placed in each location 7.

Finally, the large wafer 82 obtained is singulated, along the edges ofthe locations 78, for example by sawing, so as to obtain a plurality ofsemiconductor devices 50.

In the two examples described, being provided with a prefabricatedpassive component comprising several capacitors, only some of thecapacitors could be connected, as a function of the chip 55 used and ofthe requirements related to the operation and applications of thelatter.

According to a variant embodiment, a semiconductor device could comprisea passive component some of the capacitors of which would be connectedin series or in parallel, so as to create a resultant capacitorconnected to the chip.

According to a variant embodiment, a semiconductor device could comprisea passive component at least one of the capacitors of which would bedirectly connected to one of the external electrical connection bumps.

According to a variant embodiment, a semiconductor device could comprisea passive component at least one of the capacitors of which would bedirectly connected to another semiconductor device, for example stackedon its backside.

This disclosure is not limited to the examples described above. Manyother variant embodiments are possible without departing from the scopedefined by the appended claims.

What is claimed is:
 1. A process for fabricating a semiconductor device,comprising: placing, in at least one location on a receiving surface ofa carrier, an electrical connection frontside of at least one integratedcircuit chip and a frontside of at least one passive componentcomprising at least one conductive plate and a dielectric plate forforming a capacitor; forming on the receiving surface a layer of anencapsulation material so as to obtain, in the location, a wafercomprising an encapsulation block in which the chip and the passivecomponent are embedded and having a frontside comprising the frontsideof the chip and the frontside of the passive component; then selectivelyconnecting the at least one conductive plate to the chip, so that thecapacitor is connected to the chip.
 2. The process according to claim 1,further comprising forming at least one front electrical connectiontrack on the frontside of the wafer.
 3. The process according to claim2, further comprising: forming at least one back electrical connectiontrack on the backside of the wafer; and forming an electrical connectionvia through the wafer and forming a front electrical connection track onthe frontside of the wafer, the back track and the front track beingconnected by the electrical connection via.
 4. The process according toclaim 1, further comprising placing the passive component such that theat least one conductive plate extends perpendicular to the receivingsurface, then selectively connecting an edge of the at least oneconductive plate to the chip.
 5. The process according to claim 1,further comprising placing the passive component such that the at leastone plate extends parallel to the receiving surface.
 6. The processaccording to claim 5, further comprising: placing the passive componenthaving a dielectric plate on the receiving surface; and forming at leastone additional conductive plate on the frontside of this dielectricplate so as to form the capacitor comprising the additional conductiveplate and the at least one conductive plate separated by the firstdielectric plate.
 7. A process comprising: placing an electricalconnection frontside of an integrated circuit chip on a receivingsurface of a carrier; placing a capacitive structure comprising at leastone conductive plate and at least one dielectric plate on the receivingsurface of the carrier adjacent to the integrated circuit chip;providing an encapsulating material layer surrounding the integratedcircuit chip and the capacitive structure, the encapsulating materiallayer having a backside co-planar with a backside of the integratedcircuit chip; forming an electrical connection between the electricalconnection frontside of the integrated circuit chip and the at least oneconductive plate of the capacitive structure, the electrical connectioncomprising a via passing through the encapsulating material layer and aconnection line formed on the backside of the encapsulating materiallayer.
 8. The process of claim 7, wherein placing the capacitivestructure comprises orienting the at least one conductive plate parallelto the receiving surface of the carrier.
 9. The process of claim 8,wherein forming the electrical connection further comprises another viapassing through the encapsulating material layer between the connectionline formed on the backside of the encapsulating material layer and theat least one conductive plate.
 10. The process of claim 9, furthercomprising: removing the carrier, the electrical connection frontside ofthe integrated circuit chip being co-planar with a frontside of theencapsulating material layer; forming another conductive plate andanother electrical connection between the electrical connectionfrontside of the integrated circuit chip and the another conductiveplate, the another electrical connection comprising a connection lineformed on the frontside of the encapsulating material layer.
 11. Theprocess of claim 7, wherein placing the capacitive structure comprisesorienting the at least one conductive plate perpendicular to thereceiving surface of the carrier.
 12. The process of claim 11, whereinforming the electrical connection further comprises making an electricalconnection between the connection line formed on the backside of theencapsulating material layer and an edge of the at least one conductiveplate.
 13. The process of claim 12, wherein the capacitive structurecomprises an another conductive plate oriented perpendicular to thereceiving surface of the carrier, further comprising: removing thecarrier, the electrical connection frontside of the integrated circuitchip being co-planar with a frontside of the encapsulating materiallayer; forming another electrical connection between the electricalconnection frontside of the integrated circuit chip and the anotherconductive plate, the another electrical connection comprising aconnection line formed on the frontside of the encapsulating materiallayer.
 14. The process of claim 13, wherein forming the anotherelectrical connection further comprises making an electrical connectionbetween the connection line formed on the frontside of the encapsulatingmaterial layer and an edge of the another conductive plate.
 15. A methodfor fabricating a device having a passive component having at least onecapacitor, the method comprising: placing a frontside of an integratedcircuit chip and a frontside of the capacitor in at least one locationon a receiving surface of a carrier; encapsulating the receivingsurface, the integrated circuit chip, and the capacitor in anencapsulation layer to define an encapsulated structure having a frontsurface and a back surface; exposing a backside of at least one plate ofthe capacitor; and electrically connecting the backside of the capacitorplate to the frontside of integrated circuit chip using one or more viaswhich extend through the encapsulation layer at a location between theintegrated circuit chip and the passive component.
 16. The method ofclaim 15, wherein electrically connecting comprises: forming a firstconductive track on the front surface between the integrated circuitchip and the via; and forming a second conductive track on the backsurface between the via and the backside of the at least one plate ofthe capacitor.
 17. The method of claim 16, further comprising forming anadditional via between the second conductive track and the backside ofthe at least one plate of the capacitor.
 18. The method of claim 15,further comprising singulating the device from a wafer-scale productionof multiple same devices.
 19. The method of claim 15, wherein thecapacitor is oriented with the plate parallel to the front and backsurfaces.
 20. The method of claim 15, wherein the capacitor is orientedwith the plate perpendicular to the front and back surfaces.